The present invention relates to a circuit for detecting supply voltage conditions, especially hot socket events that occur when an integrated circuit device is inserted or removed from an electronic system while the system remains powered on. More particularly, the present invention relates to a supply voltage detection circuit suitable for detecting hot socket conditions in mixed supply voltage systems having a wide range of power supply voltage levels.
Digital electronic systems are commonly implemented by combining and interconnecting several different integrated circuit (IC) devices such as processors, memory devices and programmable logic devices. Programmable logic devices (PLDs) are standardized ICs that are readily customizable to perform desired functions. The various IC devices typically communicate with one another by way of input/output (I/O) signals transmitted over a system bus. An I/O power supply provides the necessary power for each device to drive I/O signals over the system bus. Many IC device, including several types of PLDs, also have a core power supply that provides the device with suitable power for processing signals.
System architectures may rely upon multiple supply voltage schemes, some of which are noisy and some of which are quiet. In particular, since bus controllers and other I/O circuitry are generally less sensitive and of lower speed than the core logic of an IC device, the I/O power supply signal VCCN is often more noisy than a relatively quiet core power supply signal VCC (or VCCQ) for an IC device. By separating the power supplies in this fashion, the circuitry connected to the core power supply is isolated to a considerable extent from switching and other types of noise present on the noisier I/O power supply. Increasingly, in newer IC devices, the core power supply voltage is lower than the I/O power supply voltage for that device.
Moreover, different IC devices within a digital system may operate at different supply voltage levels. As processing technology improvesxe2x80x94for instance with the scaling down of CMOS (complementary metal-oxide semiconductor) devicesxe2x80x94the power supply voltage levels required by IC devices are steadily lowering. However, devices made with newer processes still need to remain compatible with previous generations of IC devices. Furthermore, different types of IC devices may also require different power supply voltage levels. As a result, mixed voltage systems in which IC devices are powered by different supply voltages are common. In such systems, the I/O power supply must be capable of accommodating multiple voltage levels. Furthermore, the difference between the highest and lowest I/O power supply signal levels within such systems is tending to increase, as is the difference between the highest I/O and lowest core power supply levels.
This growing variation in power supply levels within an electronic system presents significant difficulties in connection with the design of an efficient and effective xe2x80x9chot socketxe2x80x9d detection circuit that can be used in IC devices having different power supply level requirements. Generally, a hot socket event may occur when an IC device is inserted in or removed from an electronic system while the system and its power supplies remain on. xe2x80x9cHotxe2x80x9d insertions or removals may be necessary and/or desirable, for example, in high-end server computers that must have minimal down-time or in systems that employ high performance plug-and-play PLDs such as solid state disks and PCMCIA cards. In these and other instances, the insertion or removal of a device may cause a hot socket condition when the power supply pins of a device have not yet reached appropriate voltage levels or when a backplane power disruption occurs. For example, when an IC device is inserted within a system, a race condition occurs between the power supply pins of the inserted device and its I/O pins. If system signals reach the I/O pins before the necessary power reaches the device""s power supply pins, the inputs and outputs may behave erratically and cause a disturbance in the system. These disturbances can adversely affect, and in some cases disable, the device as well as the rest of the system.
A supply voltage detection circuit may be used to detect and prevent the occurrence of a hot socket event and thereby improve system serviceability, reliability, and availability. When a hot socket condition is detected, the circuit activates related input/output buffer circuitry to disable an I/O pin associated with the circuit by placing the pin in a high impedance tri-state. The I/O pin remains tri-stated until appropriate supply voltage levels are reached at the IC device""s power pins. Such a hot socket detection circuit is disclosed in U.S. Pat. No. 6,040,712, for example.
When the supply signals are steady and high, it is important that only small leakage currents be generated by a hot socket detection circuit to minimize the effect on regular operation of the device and system. For example, leakage currents may be generated into or out of the supply voltage pins of the device. However, in multiple-voltage systems, particularly as power supply levels decrease (e.g., to 1.5 V or lower), it may become increasingly difficult to keep leakage currents low. Furthermore, it is also essential that a hot socket detection circuit be capable of rapidly detecting and reacting to the occurrence of a hot socket condition to minimize any possible adverse effect on the device or overall system at the onset of such an event.
Consequently, there is a need for a more effective supply voltage detection circuit capable of providing low leakage currents and rapid hot socket condition detection in IC devices having a wide range in their I/O and core power supply levels. In addition, by using the same detection circuit design for different devices with a variety of power supply specifications, lower design costs and improved efficiency can be realized.
In accordance with the present invention, a supply voltage detection circuit operates to detect a supply voltage condition, in particular a hot socket condition, when the voltage at any one of an IC device""s power supply signal pins, e.g., an I/O power supply signal VCCN or a core power supply signal VCC, is below its steady state or expected level. Hot socket conditions may occur when an IC device is inserted in or removed from an electronic system while the system remains powered on, i.e., while the I/O and core power supplies remain live. The detection circuit rapidly and effectively detects hot socket conditions for a wide range of power supply signal levels, including the low power supply signal levels that are increasingly common in newer IC devices. The detection circuit advantageously limits the size of leakage currents under steady state conditions, to minimize their effect on regular operation of the IC device and overall system.
In one aspect, the invention provides a detection circuit for an input/output terminal of an integrated circuit device. The input/output terminal may be a bidirectional terminal, a unidirectional input terminal, or a unidirectional output terminal. The circuit comprises a first voltage detection circuit having an input for receiving a first supply voltage signal and an output for providing a first detection signal. The first detection signal indicates when the voltage level of the first supply voltage signal is below a first steady state supply level. Similarly, a second voltage detection circuit has an input for receiving a second supply voltage signal and an output for providing a second detection signal that indicates when the voltage level of the second supply voltage signal is below a second steady state supply level. A logic circuit receives the first and second detection signals and provides at least one detected condition (e.g., hot socket condition) signal for disabling current flow through the input/output terminal when either the first supply voltage signal is below the first steady state supply level or the second supply voltage signal is below the second steady state supply level.
The detection circuit may further comprise a bias circuit for receiving the first supply voltage signal and a signal corresponding to the voltage at the input/output terminal. The bias circuit provides a bias power voltage signal substantially equal to the greater of the first supply voltage signal and the voltage at the input/output terminal. In one embodiment, the first voltage detection circuit is powered by the bias power voltage signal, and the second voltage detection circuit is powered by the first supply voltage signal, particularly where the first steady state supply level is greater than or equal to the second steady state supply level. The first supply voltage signal may be provided by an input/output power supply and the second supply voltage signal may be provided by a core power supply.
In one embodiment, each of the first and second voltage detection circuits includes a latch (such as a half latch) having an input and an output, with the output of the voltage detection circuit being at the input of the first latch. Each detection circuit further includes first and second transistors. The first transistor is coupled between the input of the voltage detection circuit and the output of the first latch, and the first transistor has a control terminal coupled to a power signal node for the voltage detection circuit. The second transistor is coupled between a reference supply voltage (e.g., VSS) and the input of the first latch, and the second transistor has a control terminal coupled to the input of the voltage detection circuit. To limit leakage currents, the first transistor may be a relatively weakly conducting transistor that has a lower conductivity than the second transistor.
The integrated circuit is conveniently fabricated using CMOS technology, and the first and second transistors may be NMOS transistors. The logic circuit for combining the first and second detection signals may comprise a NOR gate having those signals as inputs, and the logic circuit may also generate a pair of complementary detected condition signals that are used to tri-state the corresponding input/output terminal.